An interline transfer CCD imager contains separate photodiodes and vertical shift registers. The photodiodes are arranged in a frame comprising multiple horizontal lines each of which consists of a multiplicity of photodiodes, while each of the vertical shift registers is a repository into which the charges contained in a corresponding line of photodiodes are emptied. The shift registers constitute approximately half the total area of the imager and permit the photodiodes to be charged and emptied electrically, without any need for using a mechanical shutter. Electrically, the same gates within the interline transfer CCD imager control both the vertical shift registers and the photodiodes. Once the charges have been read out of each line of photodiodes into the corresponding vertical shift register, a sequence of vertical clock pulses is used to read the contents of each vertical shift register out of the interline transfer CCD imager in sequence. When all of the vertical shift registers have been cleared, a third level pulse (so called because its voltage level is appreciably greater in magnitude than the respective high and low levels of the remainder of the vertical clock pulse sequence) is applied to empty the photodiodes into their respective shift registers all over again.
The frame rate of a CCD imager may be increased by increasing the pixel clock frequency, by increasing the number of imager outputs, or by a combination of both. By way of example, an imager may be designed with 64 outputs and with a pixel frequency of 21 megahertz. The number of pixels per line per output of such an imager may be 17. To clock out 17 pixels at 21 megahertz, the time available for clocking out one line is only 810 nanoseconds. The horizontal retrace or line transfer time thus has to be held to 200 nanoseconds or less, the lower limit being the minimum time period during which the imager can still operate. A clock driver for such an arrangement needs to charge and discharge a 15,000 to 25,000 picofarad load with rise and fall times as short as 40 nanoseconds. The amount of leading edge current a clock driver of this type needs to supply is very large and is typically measured in amperes rather than in milliamperes.
The current I.sub.S through a switch connected to charge a capacitor from a constant current source, beginning at the instant the switch is closed, is given by the formula: EQU I.sub.S =CdV.sub.C /dt
where C is the capacitance of the capacitor and dV.sub.C /dt is the rate of change of the voltage across the capacitor with respect to time. To charge such a capacitor to 10 volts in 10 nanoseconds, the current I.sub.S is 0.1 ampere for a 100 picofarad capacitor, 1 ampere for a 1000 picofarad capacitor, 5 amperes for a 5000 picofarad capacitor, and 10 amperes for a 10,000 picofarad capacitor.
In the past, clock drivers have supplied low, high, and third levels to CCD imagers, using analog switches to set the several voltage levels and buffer amplifiers to supply the necessary current. Usually, buffer amplifiers can only supply up to 400 milliamperes maximum and have slow slew rates which are of the order of 15 volts per microsecond. Other clock drivers used in the past meet the new speed and current requirements for the low and high level voltages, but fail to meet positive and negative third level voltage requirements. Thus, the full set of speed, current, and voltage requirements for CCD imagers with which the present invention is concerned are not met with previously known drivers and a need for substantial improvement exists.
The present invention deals with the manner in which third level pulses are combined with the usual vertical clock pulses to drive high density interline transfer CCD imagers at very high frame rates with the large amounts of current required. Specifically, it deals with doing so using circuit components which are both relatively inexpensive and readily available commercially and which enable the necessary high speed, large current, and high voltage requirements to be met.